Gate driver circuits including amorphous silicon transistors (also referred to as a-Si TFTs) have been developed. Such a gate driver circuit has a problem of malfunctions due to a shift in the threshold voltage of a transistor for keeping the potential of a gate line low (at an L level) (such a transistor is also referred to as a pull down transistor). In order to solve this problem, a gate driver circuit in which a pull down transistor is repeatedly turned on and off in a period during which the potential of a gate line is kept low has been disclosed (see References 1 and 2, for example). With such a gate driver circuit, a period during which the pull down transistor is on can be shortened; thus, deterioration of the pull down transistor can be suppressed.
In addition, the gate driver circuit including amorphous silicon transistors includes a transistor for controlling timing of outputting high voltage to the gate line (such a transistor is also referred to as a pull up transistor). One of a source and a drain of the pull up transistor is connected to a clock signal line. The other of the source and the drain of the pull up transistor is connected to a gate signal line. A driving method by which the potential of a gate of the pull up transistor is made higher than the high (H-level) potential of a clock signal by capacitive coupling is employed. In order to realize the driving method, it is necessary to make the gate of the pull up transistor be in a floating state. Thus, it is necessary to turn off all the transistors that are connected to the gate of the pull up transistor.